// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.

#ifndef VERILATED_VRVCPU_H_
#define VERILATED_VRVCPU_H_  // guard

#include "verilated_heavy.h"

//==========

class Vrvcpu__Syms;
class Vrvcpu_VerilatedVcd;


//----------

VL_MODULE(Vrvcpu) {
  public:

    // PORTS
    // The application code writes and reads these signals to
    // propagate new values into/out from the Verilated model.
    VL_IN8(clock,0,0);
    VL_IN8(reset,0,0);
    VL_OUT8(io_inst_ena,0,0);
    VL_IN(io_inst,31,0);
    VL_OUT64(io_inst_addr,63,0);
    VL_OUT64(io_mem_r_data,63,0);

    // LOCAL SIGNALS
    // Internals; generally not touched by application code
    // Anonymous structures to workaround compiler member-count bugs
    struct {
        CData/*4:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_rs1_r_addr;
        CData/*4:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_rs2_r_addr;
        CData/*4:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_inst_type;
        CData/*0:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_pc_ena_j;
        CData/*0:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_pc_ena_b;
        CData/*1:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_mem_sel;
        CData/*0:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_mem_ext;
        CData/*0:0*/ rvcpu__DOT__M_RVcore__DOT__M_Branch_io_pc_ena;
        CData/*0:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage_io_mem_r_ena;
        CData/*0:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage_io_mem_w_ena;
        CData/*0:0*/ rvcpu__DOT__M_RVcore__DOT__M_WB_Stage_io_wb_w_ena;
        CData/*4:0*/ rvcpu__DOT__M_RVcore__DOT__M_WB_Stage_io_wb_w_addr;
        CData/*5:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__op2_mul_lo_lo_lo;
        CData/*4:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_14;
        CData/*5:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_22;
        CData/*7:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__op2_mul_lo_lo_13;
        CData/*4:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__op2_mul_lo_lo_lo_14;
        CData/*5:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__op2_mul_lo_lo_hi_14;
        CData/*4:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_105;
        CData/*1:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_106;
        CData/*5:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_156;
        CData/*0:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_172;
        CData/*4:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_197;
        CData/*5:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_207;
        CData/*7:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT__alu_result_lo_lo;
        CData/*7:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT__alu_result_lo_lo_1;
        CData/*7:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT__alu_result_lo_lo_2;
        CData/*7:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT__alu_result_lo_lo_3;
        CData/*7:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT__alu_result_lo_lo_4;
        CData/*7:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT__io_rd_w_data_lo_lo;
        CData/*5:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT__io_rd_w_data_lo_lo_lo_2;
        CData/*6:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT__io_rd_w_data_lo_lo_lo_4;
        SData/*11:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__imm;
        SData/*12:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__op2_mul_lo_lo;
        SData/*10:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__op2_mul_lo_lo_14;
        SData/*12:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__io_offset_lo_hi;
        SData/*11:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT__io_rd_w_data_lo_lo_2;
        SData/*13:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT__io_rd_w_data_lo_lo_4;
        IData/*31:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__op2_mul_hi_27;
        IData/*31:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___alu_result_T_32;
        IData/*31:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___alu_result_T_197;
        IData/*31:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___alu_result_T_494;
        IData/*31:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___alu_result_T_658;
        VlWide<4>/*126:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___GEN_19;
        VlWide<4>/*126:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT___GEN_50;
        QData/*63:0*/ rvcpu__DOT__M_RAM_io_mem_r_data;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_IF_Stage_io_pc_out;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_op1;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage_io_op2;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage_io_rd_data;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Branch_io_rd_data_out;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Branch_io_pc_in;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_WB_Stage_io_wb_w_data;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile_io_r_data1;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile_io_r_data2;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_IF_Stage__DOT__pc;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_IF_Stage__DOT__the_addr;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_IF_Stage__DOT___pc_T_3;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___op2_mul_T_52;
        QData/*50:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT__io_offset_hi_hi_hi_1;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_102;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_133;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_165;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_ID_Stage__DOT___GEN_200;
    };
    struct {
        QData/*62:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___alu_result_T_361;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___GEN_1;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___GEN_3;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Exe_Stage__DOT___GEN_6;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Branch__DOT___GEN_3;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT___GEN_13;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT__the_mask;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT__the_data_mask;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT___GEN_28;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT__the_data_ext;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT___GEN_29;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Mem_Stage__DOT___GEN_33;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_0;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_1;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_2;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_3;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_4;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_5;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_6;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_7;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_8;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_9;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_10;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_11;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_12;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_13;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_14;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_15;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_16;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_17;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_18;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_19;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_20;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_21;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_22;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_23;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_24;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_25;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_26;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_27;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_28;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_29;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_30;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT__regs_31;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT___GEN_117;
        QData/*63:0*/ rvcpu__DOT__M_RVcore__DOT__M_Regfile__DOT___GEN_150;
        VlUnpacked<QData/*63:0*/, 1024> rvcpu__DOT__M_RAM__DOT__Ram_Block;
    };

    // LOCAL VARIABLES
    // Internals; generally not touched by application code
    CData/*0:0*/ __Vclklast__TOP__clock;
    VlUnpacked<CData/*0:0*/, 3> __Vm_traceActivity;

    // INTERNAL VARIABLES
    // Internals; generally not touched by application code
    Vrvcpu__Syms* __VlSymsp;  // Symbol table

    // CONSTRUCTORS
  private:
    VL_UNCOPYABLE(Vrvcpu);  ///< Copying not allowed
  public:
    /// Construct the model; called by application code
    /// If contextp is null, then the model will use the default global context
    /// If name is "", then makes a wrapper with a
    /// single model invisible with respect to DPI scope names.
    Vrvcpu(VerilatedContext* contextp, const char* name = "TOP");
    Vrvcpu(const char* name = "TOP")
      : Vrvcpu(nullptr, name) {}
    /// Destroy the model; called (often implicitly) by application code
    ~Vrvcpu();
    /// Trace signals in the model; called by application code
    void trace(VerilatedVcdC* tfp, int levels, int options = 0);

    // API METHODS
    /// Return current simulation context for this model.
    /// Used to get to e.g. simulation time via contextp()->time()
    VerilatedContext* contextp();
    /// Evaluate the model.  Application must call when inputs change.
    void eval() { eval_step(); }
    /// Evaluate when calling multiple units/models per time step.
    void eval_step();
    /// Evaluate at end of a timestep for tracing, when using eval_step().
    /// Application must call after all eval() and before time changes.
    void eval_end_step() {}
    /// Simulation complete, run final blocks.  Application must call on completion.
    void final();

    // INTERNAL METHODS
    static void _eval_initial_loop(Vrvcpu__Syms* __restrict vlSymsp);
    void __Vconfigure(Vrvcpu__Syms* symsp, bool first);
  private:
    static QData _change_request(Vrvcpu__Syms* __restrict vlSymsp);
    static QData _change_request_1(Vrvcpu__Syms* __restrict vlSymsp);
  public:
    static void _combo__TOP__1(Vrvcpu__Syms* __restrict vlSymsp);
    static void _combo__TOP__4(Vrvcpu__Syms* __restrict vlSymsp);
  private:
    static void _ctor_var_reset(Vrvcpu* self) VL_ATTR_COLD;
  public:
    static void _eval(Vrvcpu__Syms* __restrict vlSymsp);
  private:
#ifdef VL_DEBUG
    void _eval_debug_assertions();
#endif  // VL_DEBUG
  public:
    static void _eval_initial(Vrvcpu__Syms* __restrict vlSymsp) VL_ATTR_COLD;
    static void _eval_settle(Vrvcpu__Syms* __restrict vlSymsp) VL_ATTR_COLD;
    static void _sequent__TOP__3(Vrvcpu__Syms* __restrict vlSymsp);
    static void _settle__TOP__2(Vrvcpu__Syms* __restrict vlSymsp) VL_ATTR_COLD;
  private:
    static void traceChgSub0(void* userp, VerilatedVcd* tracep);
    static void traceChgTop0(void* userp, VerilatedVcd* tracep);
    static void traceCleanup(void* userp, VerilatedVcd* /*unused*/);
    static void traceFullSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
    static void traceFullTop0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
    static void traceInitSub0(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
    static void traceInitTop(void* userp, VerilatedVcd* tracep) VL_ATTR_COLD;
    void traceRegister(VerilatedVcd* tracep) VL_ATTR_COLD;
    static void traceInit(void* userp, VerilatedVcd* tracep, uint32_t code) VL_ATTR_COLD;
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);

//----------


#endif  // guard
